Advanced Computer Architecture MCQs with Answers pdf for MCA, BCA and other IT courses & competitive and academic examinations.
- Computer architecture is abstracted by its _.
a. Instruction
b. Instruction set
c. Organization
d. None of the above
Ans: b - Instruction sets include-
a. Opcode
b. Addressing modes
c. Registers
d. All of the above
Ans: d - Sequential computer was improved from bit-serial to-
a. Bit-parallel
b. Byte serial
c. Word-parallel
d. None of the above
Ans: c - Von Newmann architecture is slow due to the _ execution of instructions in a program.
a. Sequential
b. Parallel
c. Non-execution
d. None of the above
Ans: a - The term ‘computer architecture’ was coined in-
a. 1972
b. 1978
c. 1964
d. 1968
Ans: c - _ levels can be used for describing a computer-
a. 1
b. 2
c. 3
d. 4
Ans: d - _ Model is more suitable for special purpose computations.
a. SIMD
b. MISD
c. MIMD
d. Both a and b
Ans: d - Hazards in pipelines can make it necessary to _ the pipeline.
a. Stall
b. Stake
c. Storm
d. None of the above
Ans: a - When a machine is pipelined, the _ execution of instructions requires pipelining of the functional unit.
a. Overloaded
b. Over rode
c. Overlapped
d. Overcrowded
Ans: c - The ratio which stays constant as performance and cost is increased by equal factors is called as-
a. Performance Ratio
b. Cost Ratio
c. Cost-Performance Ratio
d. All of the above
Ans: c - The cost-performance ratio is a good indicator of _ quality for small changes.
a. Relative
b. Absolute
c. Absolute relative
d. All of the above
Ans: a - The processors in a multiprocessor system communicate with each other through _.
a. Shared memory
b. The shared variable in a common memory
c. Both a & b
d. None of the above
Ans: b - Interprocessor communication is done through _ among nodes-
a. Shared variable
b. Shared memory
c. Message passing
d. None of the above
Ans: c - Explicit vector instructions were introduced with the appearance of _.
a. Processors
b. Micro processor
c. Intel processors
d. Vector processors
Ans: b - An SIMD computer exploits _ parallelism-
a. Spatial
b. Temporal
c. Both a & b
d. None of the above
Ans: a - Associate memory can be used to build _ associative processors.
a. SISD
b. SIMD
c. MISD
d. MIMD
Ans: b - _ architecture supports the pipelined flow of vectors operands directly from the memory to pipelines and then back to memory.
a. Memory to memory
b. Register to memory
c. Memory to register
d. Register to register
Ans: a - _ Architecture uses vector registers to interface between the memory and functional lines.
a. Memory to memory
b. Register to memory
c. Memory to register
d. Register to register
Ans: d - There are _ families of pipelined vector processors.
a. 1
b. 2
c. 3
d. 4
Ans: b - At the system level the description of the _ architecture is based on processor level building blocks.
a. Abstract
b. Concrete
c. Encapsulated
d. None of the above
Ans: b - The _ architecture of a processor often referred to as simply the architecture of the processor.
a. Abstract
b. Concrete
c. Encapsulated
d. None of the above
Ans: a - _ classification shows the architectural evolution from sequential scalar computers to vector processors and parallel computers.
a. Von-Neumann’s
b. Nyquist’s
c. Flynn’s
d. None of the above
Ans: c - Pipelining offers an economical way to realize _ parallelism in digital computers.
a. Spatial
b. Temporal
c. Concurrent
d. None of the above
Ans: b - The concept of _ processing in a computer is similar to assembly lines in an industrial plan.
a. Vector
b. Sequential
c. Pipeline
d. None of the above
Ans: c - _ are streamed into the pipe and get executed in an over-tapped fashion at the subtask level.
a. Successive tasks
b. Independent tasks
c. Concurrent tasks
d. All of the above
Ans: a - Weather modelling is _ numeric computation.
a. Structured
b. Unstructured
c. Highly-structured
d. None of the above
Ans: c - CPI stands for-
a. Clock cycles per instructions
b. Click per instructions
c. Cycles per inch
d. None of the above
Ans: a - Pipelining yields a reduction in the _ per instruction.
a. Fetching Line
b. Executions tine
c. Average execution time
d. None of the above
Ans: c - Pipelining _ the clock cycle time.
a. Decreases
b. Increases
c. Stabilizes
d. None of the time
Ans: a - In _ pipeline all tasks have equal processing time in all station facilities.
a. Delay
b. Uniform-delay
c. Non-uniform delay
d. None of the above
Ans: b - CPU of modern digital computers can generally be partitioned into _ sections.
a. 1
b. 2
c. 3
d. 4
Ans: c - Partitions of CPU is-
a. Instructions unit
b. Instruction queue
c. Execution unit
d. All of the above
Ans: d - _ is faster storage of copies of programs and data.
a. RAM
b. ROM
c. CACHE
d. Hard disk
Ans: c - Programs and data reside in the _, which usually consists of interleaved memory modules.
a. Hard disk
b. Main memory
c. Cache
d. ROM
Ans: b - _ are fast registers for holding the intermediate results.
a. Latches
b. J.K
c. RS
d. Master slave
Ans: a - The instruction queue is _ storage area-
a. FIFO
b. LIFO
c. FILO
d. All of the above
Ans: a - _ may contain multiple functional pipelines for arithmetic logic functions.
a. Instruction queue
b. Instruction unit
c. Execution unit
d. All of the above
Ans: c - _ Hazard in pipelines is caused by resource conflicts.
a. Structural
b. Data
c. Control
d. None of the above
Ans: a - _ hazards arise when an instruction depends on the results of previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.
a. Structural
b. Data
c. Control
d. None of the above
Ans: b - _ hazards arise from the pipelining of branches and other instructions the change the PC.
a. Structural
b. Data
c. Control
d. None o the above
Ans: c - Computer has gone through two major stages of development _ & _.
a. Mechanical & Electrical
b. Pipelining & Distributed
c. Electrical & Concurrency
d. Pipelining & Mechanical
Ans: a - The study of Computer architecture involves both _ organization and _ requirements.
a. Hardware & Software
b. Register & Addressing Modes
c. Assembly & operation codes
d. Software & CPU
Ans: a
43.The term Computer Architecture was coined in _ by the ‘Chief architects of the _
a. 1974, 360 System
b. 1965, AT & T
c. 1964, IBM System
d. 1984, ENCI System
Ans: c
- True/False
- The sequential computer was improved bit-serial to word- parallel operations
- The von-Neumann architecture is fast due to the sequential execution of instructions in the Program.
a. Only 1
b. Only 2
c. Both 1 & 2
d. None of the above
Ans: a - The study of architecture covers both _ and _.
a. Evolutional, Revolution
b. IBM System, Revolution
c. Instruction-set architecture, Machine implementation organizations
d. Evolutional, IBM System
Ans: c - _ Architecture supports the pipelined flow of vector operands directly from the memory to Pipelines and then back to the memory. _ Architecture uses vector registers to interface between the memory and functional Pipelines.
a. Memory –to-register, Register – to – Register
b. Memory –to-Memory, Register – to – Register
c. Memory –to-Pipelines, Register – to – Memory
d. Memory –to-register, Register – to – Pipelines
Ans: b - _ offers an economical way to realize temporal parallelism in _ computers.
a. Pipelining, Super
b. Pipelining, Digital
c. IBM System, Super
d. Evolutional, Digital
Ans: b - True/False
- Pipelining is an implementation technique where multiple instructions are overlapped in execution.
- A Pipeline is a compiler line.
a. Only 1
b. Only 2
c. Both 1 & 2
d. None of the above
Ans: a - _ is faster storage of copies of programs & data, which are ready for execution. The Cache is used to close up the speed gap between the Main memory and the _.
a. Cache Memory, CPU
b. CPU, Cache Memory
c. Primary Memory, Cache Memory
d. None of these
Ans: a - There are three classes of Hazards , & _.
a. Structural Hazards, Data Hazards, Control hazards.
b. Pipeline, System hazards, Data hazards
c. Linear, Uniform Linear, Cache
d. Pipeline, Linear, Cache
Ans: a - _ Complier must be developed to detect : The concurrency among vector instructions, which can be realized with pipelining. A _ compiler would regenerate parallelism lost in the use of sequential languages.
a. Intelligent, Vectorizing
b. Vectorizing, Intelligent
c. Parallel, Pipeline
d. Cache Memory, data hazards
Ans: a - A _ scheduling model is presented for multi-pipeline vector processes. A long vector task can be partitioned into many _.
a. Parallel task, Sub vectors.
b. Sub vectors, parallel task
c. Vectors, Pipelining
d. None of these
Ans: a - The instruction Processing Unit fetches and decodes _ and _ instructions.
a. Vector, Sub vector
b. Pipelines, parallel task
c. Scalar, Vector
d. Pipelines, Scalar
Ans: c - The superscalar issue was first formulated as early as . The superscalar processors have to issue multiple instructions per cycle, the first task necessarily is .
a. 1970, parallel decoding
b. 1975, Pipelines
c. 1980, CISC processors
d. None of these
Ans: a - Super scalar instruction issue comprises two major aspects
a. Pipelines, Superscalar
b. Vector, Sub vector
c. Issue Policy, Issue Rate
d. None of these
Ans: c - Superscalar processors have introduced intricate instruction issue policies, involving advanced techniques such as :
a. Shelving, Register naming, Speculative branch processing
b. Parallel decoding, Register naming, Shelving
c. Design space, Issue Policy, Issue Rate
d. None of these
Ans: a - A _ machine with memory – Memory
- Operations can easily be substituted by the compiler and used as a register – register machine.
- _ processors have fewer and simpler instructions than CISC processors.
a. GPR, RISC
b. RISC, GPR
c. CPU, CISC
d. RISC, CPU
Ans: a - Which specific task is not included in superscalar processing?
a. Parallel decoding
b. Superscalar instruction
c. Parallel instruction
d. Pipelines
Ans: d - Computer architecture is abstracted by its instruction set, which includes , , _ & _
a. opcode, addressing modes, registers, virtual memory
b. Pipelining, Rectorization, concurrency, opcode
c. Addressing modes, Pipelining, Register, opcode
d. Register, virtual memory, restoration, pipelining
Ans: a - _ is a standard technique for removing false date dependencies. & _ dependencies, among register data.
a. Register naming, WAR, WAW
b. WAR, WAW, shelving
c. Register naming, shelving, WAW
d. None of these